The present invention is directed to a buffer, and more particularly, a buffer capable of transferring an input signal at high speed for the case of a high-to-low transition as well as a low-to-high transition.
Conventional digital buffers are commonly optimized for fast data transfer during either a high-to-low transition or a low-to-high transition, but not both. Accordingly, when a buffer is optimized for high-speed high-to-low transitions of an input signal, a low-to-high transition in the signal output will occur at a relatively low speed. The inverse is also truexe2x80x94when a buffer is optimized for high-speed low-to-high transitions of an input signal, a high-to-low output signal transition will occur at a relatively low speed.
FIG. 1 is a circuit diagram illustrating an embodiment of a conventional buffer, comprising an inverter I1 which includes a PMOS transistor P1 and an NMOS transistor SN1, and an inverter I2 which includes a PMOS transistor SP1 and an NMOS transistor N1. As shown in FIG. 1, SN1 and SP1 denote small-sized NMOS and PMOS transistors, respectively. The small-sized NMOS transistor SN1 and PMOS transistor SP1 are provided in order to increase the signal output buffering speed in the case of a high-to-low transition of an input signal IN.
FIG. 2 is a timing diagram illustrating an operation of the circuit shown in FIG. 1. The signal output transition time is relatively fast in the case where the input signal IN transitions from a high level to a low level at a high speed (see reference 92). On the contrary, the transition time is relatively slow in case where the input signal IN transitions from a low level to a high level (see reference 94).
FIG. 3 is a circuit diagram illustrating another embodiment of a conventional buffer, comprising an inverter I3 which includes a PMOS transistor SP2 and an NMOS transistor N2, and an inverter I4 which includes a PMOS transistor P2 and an NMOS transistor SN2. As shown in FIG. 3, SN2 and SP2 denote small-sized NMOS and PMOS transistors, respectively. The small-sized NMOS transistor SN2 and PMOS transistor SP2 are provided in order to increase the signal output buffering speed in the case of a low-to-high transition of an input signal IN.
FIG. 4 is a timing diagram explaining an operation of the circuit shown in FIG. 3. The signal output transition time is relatively fast in the case where the input signal IN transitions from a low level to a high level at a high speed (see reference 96). On the contrary, the transition time is relatively slow in case where the input signal IN transitions from a high level to a low level (see reference 98).
In this manner, the conventional buffer is capable of relatively fast signal propagation of the output signal OUT in either case of a low-to-high transition or a high-to-low transition of the input signal IN. However, the conventional buffer is not capable of efficient propagation of both low-to-high and high-to-low transitions of the input signal IN.
It is an object of the present invention to provide a buffer suitable for increasing speed in generation of a signal output for both cases of a high-to-low transition and a low-to-high transition of an input signal.
In one aspect, the present invention comprises a buffer, comprising a pull-down means for generating an output signal that transitions to a first state when an input signal transitions from a first state to a second state in response to a control signal of a first control state. A pull-up means generates the output signal that transitions to a second state when the input signal transitions from the second state to the first state in response to the control signal being of a second control state. A control signal generator generates the control signal in response to the state of the output signal.
In a preferred embodiment, the pull-down means comprises a first pull-up transistor having a source to which a power supply is applied, and a gate to which the control signal is applied. A second pull-up transistor has a source which is connected to a drain of the first pull-up transistor, a gate to which the input signal is applied, and a drain which generates the output signal. A first pull-down transistor includes a drain which is connected to the drain of the second pull-up transistor, and a gate to which the input signal is applied. A second pull-down transistor includes a drain which is connected to a source of the first pull-down transistor, a gate to which an inverted signal of the control signal is applied, and a source to which a ground voltage is applied, the second pull-up transistor being smaller than the first pull-up transistor and the first and second pull-down transistors.
In another preferred embodiment, wherein the pull-up means comprises a third pull-up transistor having a gate to which the inverted signal of the control signal is applied, and a source to which a power supply is applied. A fourth pull-up transistor includes a source which is connected to the drain of the third pull-up transistor, a gate to which the input signal is applied, and a drain in which the output signal is generated. A third pull-down transistor includes a source which is connected to the drain of the fourth pull-up transistor, and a gate to which the input signal is applied. A fourth pull-down transistor includes a drain which is connected to the source of the third pull-down transistor, a gate to which the control signal is applied, and a source to which a ground voltage is applied, the third pull-down transistor being smaller than the third and fourth pull-up transistors and the fourth pull-down transistor.
In another preferred embodiment, the pull-down means comprises a fifth pull-up transistor having a source to which a power supply is applied, and a gate to which the input signal is applied. A fifth pull-down transistor includes a drain which is connected to a drain of the fifth pull-up transistor, a gate to which the input signal is applied, and a source which is connected to a ground voltage. A first CMOS transfer gate transfers a signal output from the drain of the fifth pull-down transistor as the output signal in response to the control signal being in a first state, the fifth pull-up transistor being smaller than the fifth pull-down transistor.
In another preferred embodiment, the pull-up means comprises a sixth pull-up transistor having a source to which a power supply is applied, and a gate to which the input signal is applied. A sixth pull-down transistor includes a drain which is connected to a drain of the sixth pull-up transistor, a gate to which the input signal is applied, and a source which is connected to a ground voltage. A second CMOS transfer gate transfers a signal output from the drain of the sixth pull-up transistor as the output signal in response to the control signal being in a second control state, the sixth pull-down transistor being smaller than the sixth pull-up transistor.
The control signal generator preferably comprises a first inverter for inverting the output signal of the pull-up or pull-down means. A delay means generates the control signal by delaying an output signal of the first inverter for a predetermined time duration. A second inverter generates the inverted control signal by inverting an output signal of the delay means.
In another aspect, the present invention is directed to a buffer comprising a pull-down means for pulling down an input signal, and for generating an output signal in response to a control signal and an inverted signal of the control signal. A pull-up means pulls-up the input signal and generates the output signal in response to signals with an opposite phase of the control signal and the inverted signal of the control signal. A control signal generator generates the control signal and the inverted signal of the control signal in response to the output signal.
In another aspect, the present invention is directed to a buffer comprising a pull-down means for outputting a pull-down signal which, in response to an input signal undergoing a transition from a low state to a high state, generates an output signal that is pulled down from a high state to a low state, and, in response to an input signal undergoing a transition from a high state to a low state, generates an output signal that is pulled up from a low state to a high state, the pull-down of the output signal occurring at a faster rate than the pull-up of the output signal, the pull-down means being activated in response to a control signal being in a first control state. A pull-up means for outputs a pull-up signal which, in response to an input signal undergoing a transition from a low state to a high state, generates an output signal that is pulled down from a high state to a low state, and, in response to an input signal undergoing a transition from a high state to a low state, generates an output signal that is pulled up from a low state to a high state, the pull-up of the output signal occurring at a faster rate than the pull-down of the output signal, the pull-down means being activated in response to the control signal being in a second control state. A control signal generator generates the control signal as a function of the output signal.